A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips(VLSI Architecture for Communication/Server Systems,<Special Section>VLSI Technology toward Frontiers of New Market)
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概要
- 論文の詳細を見る
Broadcast and synchronization techniques are used for cache coherence control in conventional larger scale snoop-based SMP systems. The penalty for synchronization is directly proportional to system size. Meanwhile, advances in LSI technology now enable placing a memory controller on a CPU die. The latency to access directly linked memory is drastically reduced by an on-die controller. Developing an enterprise server system with these CPUs allows us an opportunity to achieve higher performance. Though the penalty of synchronization is counted whenever a cache miss occurs, it is necessary to improve the coherence method to receive the full benefit of this effect. In this paper, we demonstrate a coherence directory organization that fits into DSM enterprise server systems. Originally, a directory-based method was adopted in high performance computing systems because of its huge scalability in comparison with snoop-based method. Though directory capacity miss and long directory access latency are the major problems of this method, the relaxed scalability requirement of enterprise servers is advantageous to us to solve these problems along with an advanced LSI technology. Our proposed directory solves both problems by implementing a full bit vector level map of the coherence directory on an LSI chip. Our experimental results validate that a system controlled by our proposed directory can surpass a snoop-based system in performance even without applying data localization optimization to an online transaction processing (OLTP) workload.
- 社団法人電子情報通信学会の論文
- 2007-10-01
著者
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Murakami Kazuaki
Kyushu
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Katsuno Akira
Fujitsu Laboratories Ltd.
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SAKAMOTO Mariko
FUJITSU LIMITED
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SUGIZAKI Go
FUJITSU LIMITED
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YOSHIDA Toshio
FUJITSU LIMITED
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INOUE Aiichiro
FUJITSU LIMITED
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INOUE Koji
Kyushu University
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Sakamoto M
Fujitsu Limited
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