An implementation of a fault-tolerant 2D systolic array on an FPGA and its evaluation (ディペンダブルコンピューティング)

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概要

• 論文の詳細を見る

• A fault-tolerant self-reconfigurable 2D systolic array to calculate matrix multiplications is implemented on an FPGA. The array uses a 1.5-track switching network for reconfiguration. The array implemented is compared with the corresponding non-redundant case by simulations for concrete examples, in terms of hardware size, total array reliability considering not only faults of processing elements but also faults in the switching networks, fabrication-time cost and computation time. Then it is shown that the fault-tolerant array is better than the corresponding non-redundant one, in terms of fabrication-time cost and the total array reliability, even if faults of switching networks are not negligible, by giving the concrete data. The results must be useful not only to realize the higher-level video stream applications, but also to design fault-tolerant 2D arrays.

• 社団法人電子情報通信学会の論文
• 2008-10-13

著者

• Takanami Itsuo

  Ichinoseki National College Of Technology In Former Times

• Takanami Itsuo

  Ichinoseki National College Of Technology

• HORITA Tadayoshi

  Department of Information and Computer Science, Polytechnic University

• Horita Tadayoshi

  Department Of Information And Computer Science Polytechnic University

• Horita Tadayoshi

  Department Of Information And Computer Science Polytechnic Univerity

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• An implementation of a fault-tolerant 2D systolic array on an FPGA and its evaluation (ディペンダブルコンピューティング)
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• A Graph-Theoretic Approach to Minimizing the Number of Dangerous Processors in Fault-Tolerant Mesh-Connected Processor Arrays(Special Issue on Function Integrated Information Systems)
• An FPGA Implementation of a Self-Reconfigurable System for the 1 1/2 Track-Switch 2-D Mesh Array with PE Faults

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