An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches

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概要

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• This paper deals with redundant 3D mesh processor arrays using 1.5-track switches, considering track and switch faults together with processor faults. Four variants are defined based on the distributions of spare PEs, and arrays of three variants have the same PE redundancies among them, but the fabrication-time costs are different. We investigate in detail how the reliability of a total system changes according to the reliabilities of tracks and switches as well as PEs, and show the concrete values of Mt and Ms, when the reliability of array are almost the same even if its variant is changed, and when it is not so, respectively, where Mt and Ms are the ratio of the hardware complexities of a PE and a track, and that of a PE and a contact point of a switch, respectively. Other results which are effective basis for the design of fault-tolerant 3D PE arrays using 1.5-TSs are given.

• （社）電子情報通信学会の論文
• 2008-02-01

著者

• HORITA Tadayoshi

  Department of Information and Computer Science, Polytechnic University

• KATOU Yuuji

  Department of Information and Computer Science, Polytechnic University

• Katou Yuuji

  Department Of Information And Computer Science Polytechnic University

• Horita Tadayoshi

  Department Of Information And Computer Science Polytechnic Univerity

• TAKANAMI Itsuo

  The Institute of Electronics, Information and Communication Engineers

関連論文

• An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches
• An implementation of a fault-tolerant 2D systolic array on an FPGA and its evaluation (ディペンダブルコンピューティング)
• An Efficiently Self-Reconstructing Array System Using E-11/2-Track Switches(Fault Tolerance)
• Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant

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