An Efficiently Self-Reconstructing Array System Using E-11/2-Track Switches(Fault Tolerance)

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概要

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• The E-11/2-track switch torus array model and the "EAR" reconfiguration method are proposed for fault tolerance of mesh or torus-connected processor arrays, where the original idea of EAR is in EAM. The comparison among these and others is described in terms of the (run-time) array reliability, hardware overhead, and/or reconfiguration time. When a designer chooses one among fault tolerant methods, he should consider their features synthetically case by case, and we consider that the results given by this paper are useful for the choice.

• 社団法人電子情報通信学会の論文
• 2003-12-01

著者

• Takanami Itsuo

  Ichinoseki National College Of Technology

• HORITA Tadayoshi

  Department of Information and Computer Science, Polytechnic University

• Horita Tadayoshi

  Department Of Information And Computer Science Polytechnic Univerity

関連論文

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• Self-Reconfiguring of 1 1/2-Track-Switch Mesh Arrays with Spares on One Row and One Column by Simple Built-in Circuit(Dependable Computing)
• An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches
• An implementation of a fault-tolerant 2D systolic array on an FPGA and its evaluation (ディペンダブルコンピューティング)
• An Efficiently Self-Reconstructing Array System Using E-11/2-Track Switches(Fault Tolerance)
• Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant
• A System for Efficiently Self-Reconstructing 11/2-Track Switch Torus Arrays
• A Graph-Theoretic Approach to Minimizing the Number of Dangerous Processors in Fault-Tolerant Mesh-Connected Processor Arrays(Special Issue on Function Integrated Information Systems)
• An FPGA Implementation of a Self-Reconfigurable System for the 1 1/2 Track-Switch 2-D Mesh Array with PE Faults

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