An FPGA Implementation of a Self-Reconfigurable System for the 1 1/2 Track-Switch 2-D Mesh Array with PE Faults

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概要

• 論文の詳細を見る

• We gave in [1] the software and hardware algorithms for reconfiguring 11/2-track switch 2-D mesh arrays with faults of processing elements, avoiding them. This paper shows an implementation of the hardware algorithm using an FPGA device, and by the logical simulation confirms the correctness of the behavior and evaluates reconfiguration time. From the result it is found that a self-repairable system is realizable and the system is useful for the run-time as well as fabrication-time reconfiguration because it requires no host computer to execute the reconfiguration algorithm and the reconfiguration time is very short.

• 社団法人電子情報通信学会の論文
• 2000-08-25

著者

• Takanami Itsuo

  Ichinoseki National College Of Technology

• HORITA Tadayoshi

  the Faculty of Engineering, Iwate University

• Horita Tadayoshi

  The Faculty Of Engineering Iwate University

関連論文

• A Novel Learning Algorithm Which Makes Multilayer Neural Networks Multiple-Weight-Fault Tolerant(Dependable Systems)(Dependable Computing)
• Self-Reconfiguring of 1 1/2-Track-Switch Mesh Arrays with Spares on One Row and One Column by Simple Built-in Circuit(Dependable Computing)
• An implementation of a fault-tolerant 2D systolic array on an FPGA and its evaluation (ディペンダブルコンピューティング)
• An Efficiently Self-Reconstructing Array System Using E-11/2-Track Switches(Fault Tolerance)
• An Efficiently Reconfigurable Architecture for Mesh-Arrays with PE and Link Faults
• A System for Efficiently Self-Reconstructing 11/2-Track Switch Torus Arrays
• A Graph-Theoretic Approach to Minimizing the Number of Dangerous Processors in Fault-Tolerant Mesh-Connected Processor Arrays(Special Issue on Function Integrated Information Systems)
• An FPGA Implementation of a Self-Reconfigurable System for the 1 1/2 Track-Switch 2-D Mesh Array with PE Faults

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