A System for Efficiently Self-Reconstructing 11/2-Track Switch Torus Arrays
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概要
- 論文の詳細を見る
A mesh-connected processor array consists of many similar processing elements(PEs), which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, it is necessary to consider some fault tolerant issues to enhance the(fabrication-time)yield and the(run-time)reliability. In this paper, we introduce the 11/2-track switch torus array by changing the connections in 11/2-track switch mesh array, and we apply our approximate reconfiguration algorithm to the torus array. We describe the reconfiguration strategy for the 11/2-track switch torus array and its realization using WSI, especially 3-dimensional realization. A hardware realization of the algorithm is proposed and simulation results about the array reliability are shown. These imply that a self-reconfigurable system with no host computer can be realized using our method hence our method is effective in enhancing the run-time reliability as well as the fabrication-time yield of processor arrays.
- 社団法人電子情報通信学会の論文
- 2001-12-01
著者
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Takanami Itsuo
Ichinoseki National College Of Technology
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HORITA Tadayoshi
the Dept.of Information and Computer Science, Polytechnic University
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Horita Tadayoshi
The Dept.of Information And Computer Science Polytechnic University
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