Retention Time Analysis on DRAM Cell Transistor from Planar to Nonplanar Gate Structures(Session 4 Silicon Devices II,AWAD2006)
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概要
- 論文の詳細を見る
We examined the characteristics of the DRAM cell transistor's retention time by extracting the electric field peak values and their positions using a new simulation method with traps. In order to enhance the retention time, it is essential to reduce the electric field at the storage node junction, which should be performed by decrease the channel doping level without any change in the threshold voltage. We compared the planar gate structure with the non-planar, and the symmetric doping profiles with the asymmetric ones.
- 社団法人電子情報通信学会の論文
- 2006-06-26
著者
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Kang Myung
R&d Division Hynix Semiconductor Inc.
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Seo Moon
R&d Division Hynix Semiconductor Inc.
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Yoo Sang
R&d Division Hynix Semiconductor Inc.
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Park Sung
R&d Division Hynix Semiconductor Inc.
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Hong Sung
R&d Division Hynix Semiconductor Inc.
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Choi Jae
R&d Division Hynix Semiconductor Inc.
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CHOI Jae
R&D Division, Hynix Semiconductor Inc.
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KIM Sang
R&D Division, Hynix Semiconductor Inc.
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YOO Sang
R&D Division, Hynix Semiconductor Inc.
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CHA Seon
R&D Division, Hynix Semiconductor Inc.
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SEO Moon
R&D Division, Hynix Semiconductor Inc.
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KWON Eun
R&D Division, Hynix Semiconductor Inc.
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KANG Myung
R&D Division, Hynix Semiconductor Inc.
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PARK Sung
R&D Division, Hynix Semiconductor Inc.
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HONG Sung
R&D Division, Hynix Semiconductor Inc.
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Cha Seon
R&d Division Hynix Semiconductor Inc.
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Kwon Eun
R&d Division Hynix Semiconductor Inc.
関連論文
- Retention Time Analysis on DRAM Cell Transistor from Planar to Nonplanar Gate Structures(Session 4 Silicon Devices II,AWAD2006)
- Retention Time Analysis on DRAM Cell Transistor from Planar to Nonplanar Gate Structures(Session 4 Silicon Devices II,AWAD2006)
- Retention Time Analysis on DRAM Cell Transistor from Planar to Nonplanar Gate Structures
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