Retention Time Analysis on DRAM Cell Transistor from Planar to Nonplanar Gate Structures
スポンサーリンク
概要
- 論文の詳細を見る
- 2006-06-26
著者
-
Kang Myung
R&d Division Hynix Semiconductor Inc.
-
Seo Moon
R&d Division Hynix Semiconductor Inc.
-
Yoo Sang
R&d Division Hynix Semiconductor Inc.
-
Park Sung
R&d Division Hynix Semiconductor Inc.
-
Choi Jae
R&d Division Hynix Semiconductor Inc.
-
CHOI Jae
R&D Division, Hynix Semiconductor Inc.
-
KIM Sang
R&D Division, Hynix Semiconductor Inc.
-
YOO Sang
R&D Division, Hynix Semiconductor Inc.
-
CHA Seon
R&D Division, Hynix Semiconductor Inc.
-
SEO Moon
R&D Division, Hynix Semiconductor Inc.
-
KWON Eun
R&D Division, Hynix Semiconductor Inc.
-
KANG Myung
R&D Division, Hynix Semiconductor Inc.
-
PARK Sung
R&D Division, Hynix Semiconductor Inc.
-
HONG Sung
R&D Division, Hynix Semiconductor Inc.
-
Cha Seon
R&d Division Hynix Semiconductor Inc.
-
Kwon Eun
R&d Division Hynix Semiconductor Inc.
関連論文
- Retention Time Analysis on DRAM Cell Transistor from Planar to Nonplanar Gate Structures(Session 4 Silicon Devices II,AWAD2006)
- Retention Time Analysis on DRAM Cell Transistor from Planar to Nonplanar Gate Structures(Session 4 Silicon Devices II,AWAD2006)
- Retention Time Analysis on DRAM Cell Transistor from Planar to Nonplanar Gate Structures
- Novel threshold voltage fine control method for FETs within a wafer using LDSi (Locally Differentiated Scanning ion implant)
- Mechanical stress issues in semiconductor technology (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Characteristics and the Model of Resistive Random Access Memory Switching of the Ti/TiO2 Resistive Material Depending on the Thickness of Ti
- Mechanical stress issues in semiconductor technology (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))