Gate Stack Architecture Analysis and Channel Engineering in Deep Sub-Micron MOSFETs
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概要
- 論文の詳細を見る
- 社団法人応用物理学会の論文
- 1999-04-30
著者
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Woo Jason
Department Of Electrical Engineering University Of California
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Cheng B
Inst. Of Physics And Center For Condensed Matter Physics Chinese Acad. Of Sci. Beijing Chn
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INANI Anand
Department of Electrical Engineering, University of California
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RAO Ramgopal
Currently with Department of Electrical Engineering, Indian Institute of Technology
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CHENG Baohong
Currently with APRDL
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Rao Ramgopal
Currently With Department Of Electrical Engineering Indian Institute Of Technology
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Inani Anand
Department Of Electrical Engineering University Of California
関連論文
- Inherent Suppression of Low-Frequency Noise Overshoot in Sub-Micron Partially-Depleted Floating Body Silicon-On-Sapphire (SOS) MOSFETs
- High-Mobility p-Channel Metal-Oxide-Semiconductor Field-Effect-Transistor on Strained Si
- Distortion Analysis of SOI MOSFETs for Analog Applications
- Improvement in Low Temperature CMOS Performance Using Retrograded Channel Profiling
- Gate Stack Architecture Analysis and Channel Engineering in Deep Sub-Micron MOSFETs
- Source/Drain Extension-to-Gate Overlap Scaling in Deep Sub-Micron MOSFETs
- A Surrounding-Gate Transistor with Multi-Pillar Silicon Channels
- Analog Performance of Asymmetric Schottky Tunneling Source nFET for RF and Mixed-Mode Application
- Modeling of the Series Resistance for Below 100nm MOSFET Regime
- A Novel Simplified Process for Self Aligned Planar Wrapping Gate FET's with Directionally Crystallized Si Channel Processed via Sequential Lateral Solidification
- Nanoscale MOSFET with Split-Gate Design for RF/Analog Application