Improvement of Written-State Retentivity by Scaling Down MNOS Memory Devices : Silicon Devices and Process Technologies(<Special Section>Solid State Devices and Materials 1)

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概要

• 論文の詳細を見る

• New MNOS retention characteristic phenomena are demonstrates. Shrunk MNOS memory devices are closely evaluated. While charge retentivity of the erased state depends only slightly on silicon nitride thickness, written -state retentivity is improved by reducing silicon nitride thickness. These new phenomena are applied to memory device design. A 1 M bit MNOS EEPROM can be designed with silicon nitride thickness 20.0 nm and programming voltage 10.7 V. These results show the MNOS memory device to be a very promising candidate for Megabit EEPROM's.

• 社団法人応用物理学会の論文
• 1988-11-20

著者

• KAMIGAKI Yoshiaki

  Central Research Laboratory, Hitachi, Ltd.

• Hagiwara Takaaki

  Musashi Works Hitachi Ltd.

• Minami Shin'ichi

  Semiconductor & Integrated Circuits Hitachi Ltd. C

• Furusawa Kazunori

  The Semiconductor &amp Integrated Circuits Div. Hitachi Ltd.

• Kamigaki Yoshiaki

  Central Research Laboratory Hitachi Ltd.

• MINAMI Shin-ichi

  Central Research Laboratory, Hitachi Ltd.

• UCHIDA Ken

  Musashi Works, Hitachi Ltd.

• FURUSAWA Kazunori

  Musashi Works, Hitachi Ltd.

• Uchida Ken

  Musashi Works Hitachi Ltd.

関連論文

• A 3 Volt 1 Mbit Full-Featured EEPROM Using a Highly-Reliable MONOS Device Technology (Special Section on High Speed and High Density Multi Functional LSI Memories)
• Defect Termination by Nitrogen Bonding due to NO Nitridation in MOS Structures
• MNOS Nonvolatile Semiconductor Memory Technology : Present and Future(Special Issue on Nonvolatile Memories)
• Improvement of Written-State Retentivity by Scaling Down MNOS Memory Devices : Silicon Devices and Process Technologies(Solid State Devices and Materials 1)
• Effects of High Temperature Hydrogen Annealing on n-Channel Si-Gate MNOS Devices : A-5: MEMORY DEVICES

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