A 3 Volt 1 Mbit Full-Featured EEPROM Using a Highly-Reliable MONOS Device Technology (Special Section on High Speed and High Density Multi Functional LSI Memories)
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概要
- 論文の詳細を見る
A low-voltage operation and highly-reliable nonvoltatile semiconductor memory with a large capacity has been manufactured using 0.8-μm CMOS technology. This 3-volt, 1-Mbit, full-featured MONOS EEPROM has a chip size of 51.3 mm^2 and a memory cell size of 23.1 μm^2. An asymmetric programming voltage method fully exploits the abilities of the MONOS device and provides 10-year data retention after 10^6 erase/write cycles. Because of its wide-margin circuit design, this EEPROM can also be operated at 5 volts. High-speed read out is provided by using the polycide word line and the differential sense amplifier with a MONOS dummy memory. New functions such as data protection with software and programming-end indication with a toggle bit are added, and chips are TSOP packaged for use in many kinds of portable equipment.
- 社団法人電子情報通信学会の論文
- 1994-08-25
著者
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Komori Kazuhiro
The Semiconductor & Integrated Circuits Div. Hitachi Ltd.
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Minami Shin-ichi
the Central Research Laboratory, Hitachi, Ltd.
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Ujiie Kazuaki
the Hitachi ULSI Engineering Corporation
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Terasawa Masaaki
the Hitachi ULSI Engineering Corporation
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Furusawa Kazunori
the Semiconductor & Integrated Circuits Div., Hitachi, Ltd.
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Kamigaki Yoshiaki
the Central Research Laboratory, Hitachi, Ltd.
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KAMIGAKI Yoshiaki
Central Research Laboratory, Hitachi, Ltd.
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Uchida K
The Hitachi Ulsi Engineering Corporation
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Minami Shin'ichi
Semiconductor & Integrated Circuits Hitachi Ltd. C
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Furusawa Kazunori
The Semiconductor & Integrated Circuits Div. Hitachi Ltd.
関連論文
- A 3 Volt 1 Mbit Full-Featured EEPROM Using a Highly-Reliable MONOS Device Technology (Special Section on High Speed and High Density Multi Functional LSI Memories)
- Defect Termination by Nitrogen Bonding due to NO Nitridation in MOS Structures
- MNOS Nonvolatile Semiconductor Memory Technology : Present and Future(Special Issue on Nonvolatile Memories)
- Improvement of Written-State Retentivity by Scaling Down MNOS Memory Devices : Silicon Devices and Process Technologies(Solid State Devices and Materials 1)