Surface State Formation during Long-Term Bias-Temperature Stress Aging of Thin SiO_2-Si Interfaces

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概要

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• Surface state formation during bias-temperature (BT) stress aging is investigated in polycrystalline silicon (phosphorous doped)-thin SiO_2-silicon capacitor fabricated by the standard silicon gate process. The applied stress field was 2.3-4.5 MV/cm. The stress temperature was 150-325℃, and the aging time was 2000 hours. Surface state density distributions were calculated using the quasi-static C-V technique. A slow increase in the sharp surface state density peak at 0.7eV above the valence band edge without measurable flat-band voltage shift is observed after positive BT stress aging, while a rapid increase in the broad peak at 0.4eV is observed after negative BT stress aging. The observed relation between the rate of change of surface state density and the stress field suggests that surface states may be induced by hot electrons injected into the oxide from P-type silicon by the Schottky process.

• 社団法人応用物理学会の論文
• 1979-06-05

著者

• Shiono Noboru

  Musashino Electrical Communication Laboratory Nippon Telegraph And Telephone Public Corporation

• Yashiro Takehisa

  Musashino Electrical Communication Laboratory Nippon Telegraph And Telephone Public Corporation

関連論文

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• Surface State Formation during Long-Term Bias-Temperature Stress Aging of Thin SiO_2-Si Interfaces
• Properties of MNMOS Structure Interposing Platinum at Si_3N_4-SiO_2 Interface
• Effect of Platinum Particles in Dual SiO_2 Interface on Charge Storage Properties
• Emitter Perimeter-to-Area Ratio Effects on High-Frequency Transistor Current Gain and Its Degradation

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