Implementation of 155.52Mbps Physical Layer Processor for ATM Applications
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概要
- 論文の詳細を見る
For a broad-band ISDN the development of ATM technology is essential. The physical layer processor is one of the standard core components in user network interface (UNI) or network node interface (NNI) of ATM switching system and is located between the optical module and the ATM layer protocol. The chip consists of two analog PLLs for 155Mbps data recovery and transmission and STM-1/STS-3c framer for ATM cell transport that satisfies the recommendations of ITU-T and ATM Forum. It is an analog/digital mixed-sigpal IC and implemented using 0.8μm digital CMOS process technology.
- 社団法人電子情報通信学会の論文
- 1997-07-24
著者
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Kim Sung-Do
Micro Electronics Technology Lab., Electronics and Telecommunications Research Institute
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Kim Sung-do
Micro Electronics Technology Lab. Electronics And Telecommunications Research Institute
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Kim Sung-do
Semiconductor Technology Division Etri
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Jung Hee-Bum
Semiconductor Technology Division, ETRI
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Kim Kui-Dong
Semiconductor Technology Division, ETRI
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Chai Sang-Hoon
Semiconductor Technology Division, ETRI
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Song Won-Chul
Semiconductor Technology Division, ETRI
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Kim Kyung-Soo
Semiconductor Technology Division, ETRI
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Kim Kyung-soo
Semiconductor Div. Electronics And Telecommunications Research Institute
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Kim Kyung-soo
Semiconductor Division Electronics And Telecommunications Research Institute
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Kim Kui-dong
Semiconductor Technology Division Etri
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Chai Sang-hoon
Semiconductor Technology Division Etri
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Song Won-chul
Semiconductor Technology Division Etri
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Jung Hee-bum
Semiconductor Technology Division Etri
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Kim K‐s
Semiconductor Technology Division Etri
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