Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits(<Special Issue>Special Section on Papers Selected from ITC-CSCC 2002)
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概要
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The interconnection problem of binary circuits becomes seriously as the exponential growth of the circuits complexity has been driven by a combination of down scaling of the device size and up scaling of the chip size. Motivated by the problem, there is much research of circuits based on multiple-valued logic. On the other hand, caused by the signal propagation delay, there exist hazards in binary logic circuits. To analyze hazards in binary logic circuits, many multiple-valued logics have been proposed, and studied on their mathematical properties. The paper will discuss on a multiple-valued logic which is suitable for treating static hazards in multiple-valued logic circuits. Then, the paper will show that the prime implicants expressions of γ-valued logic functions realize static hazards free γ-valued logic circuits.
- 社団法人電子情報通信学会の論文
- 2003-06-01
著者
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TAKAGI Noboru
Department of Management and Information Science, Nagasaki Insutitute of Applied Science
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Takagi Noboru
Department Of Electronics And Informatics Faculty Of Engineering Toyama Prefectural University
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NAKASHIMA Kyoichi
Department of Electronics and Informatics, Faculty of Engineering, Toyama Prefectural University
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Nakashima Kyoichi
Department Of Electronics And Informatics Faculty Of Engineering Toyama Prefectural University
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- Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits(Special Section on Papers Selected from ITC-CSCC 2002)
- Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits
- A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations
- A Logical Model for Representing Ambiguous States in Multiple-Valued Logic Systems