Takagi Noboru | Department Of Electronics And Informatics Faculty Of Engineering Toyama Prefectural University

スポンサーリンク

概要

• TAKAGI Noboruの詳細を見る
• 同名の論文著者
• Department Of Electronics And Informatics Faculty Of Engineering Toyama Prefectural Universityの論文著者

関連著者

• Takagi Noboru

  Department Of Electronics And Informatics Faculty Of Engineering Toyama Prefectural University

• TAKAGI Noboru

  Department of Management and Information Science, Nagasaki Insutitute of Applied Science

• Nakashima Kyoichi

  Department Of Electronics And Informatics Faculty Of Engineering Toyama Prefectural University

• NAKASHIMA Kyoichi

  Department of Electronics and Informatics, Faculty of Engineering, Toyama Prefectural University

• Mukaidono Masao

  Department of Computer Science, Meiji University

• Tokinaga Shozo

  Graduate School Of Economics Kyushu University

• Tokinaga Shozo

  Graduate School Economics Kyushu University

• Mukaidono Masao

  Meiji University

• Mukaidono Masao

  Department Of Computer Science Faculty Of Science And Technology Meiji University

• Mukaidono M

  Meiji Univ. Kawasaki‐shi Jpn

• Takagi N

  Toyama Prefectural Univ. Toyama‐shi Jpn

• Nakashima K

  Toyama Prefectural Univ. Toyama‐shi Jpn

• Nakashima Kyoichi

  Department Of Electronics And Informatics Toyama Prefectural University

• Takagi Noboru

  Department Of Intelligent Systems Design Engineering Toyama Prefectural University

• Takagi Noboru

  Department Of Management And Information Science Nagasaki Insutitute Of Applied Science

• Takagi Noboru

  Department Of Electronics And Informatics Toyama Prefectural University

もっと見る 閉じる

著作論文

• Decomposition of Surface Data into Fractal Signals Based on Mean Likelihood and Importance Sampling and Its Applications to Feature Extraction(Digital Signal Processing)
• A Fail-Safe Condition for Multiple-Valued Logic Circuits Consisting of AND, OR and NOT Gates
• A Necessary and Sufficient Condition for Kleenean Functions
• Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits(Special Section on Papers Selected from ITC-CSCC 2002)
• A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations
• A Logical Model for Representing Ambiguous States in Multiple-Valued Logic Systems

スポンサーリンク