A Fail-Safe Condition for Multiple-Valued Logic Circuits Consisting of AND, OR and NOT Gates
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概要
- 論文の詳細を見る
- 社団法人電子情報通信学会の論文
- 2002-11-01
著者
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TAKAGI Noboru
Department of Management and Information Science, Nagasaki Insutitute of Applied Science
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Takagi Noboru
Department Of Electronics And Informatics Faculty Of Engineering Toyama Prefectural University
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NAKASHIMA Kyoichi
Department of Electronics and Informatics, Faculty of Engineering, Toyama Prefectural University
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Nakashima Kyoichi
Department Of Electronics And Informatics Faculty Of Engineering Toyama Prefectural University
関連論文
- Decomposition of Surface Data into Fractal Signals Based on Mean Likelihood and Importance Sampling and Its Applications to Feature Extraction(Digital Signal Processing)
- A Fail-Safe Condition for Multiple-Valued Logic Circuits Consisting of AND, OR and NOT Gates
- A Necessary and Sufficient Condition for Kleenean Functions
- Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits(Special Section on Papers Selected from ITC-CSCC 2002)
- Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits
- A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations
- A Logical Model for Representing Ambiguous States in Multiple-Valued Logic Systems