A Logical Model for Representing Ambiguous States in Multiple-Valued Logic Systems
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概要
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In this paper, we focus on regularity and setvalued functions. Regularity was first introduced by S. C. Kleene in the propositional operations of his ternary logic. Then, M. Mukaidono investigated some properties of ternary functions, which can be represented by regular operations. He called such ternary functions "regular ternary logic functions". Regular ternary logic functions are useful for representing and analyzing ambiguities such as transient states or initial states in binary logic circuits that Boolean functions cannot cope with. Furthermore, they are also applied to studies of fail-safe systems for binary logic circuits. In this paper, we will discuss an extension of regular ternary logic functions into r-valued set-valued functions, which are defined as mappings on a set of nonempty subsets of the r-valued set {0,1,...,r-1}. First, the paper will show a method by which operations on the r-valued set {0,1,...,r-1} can be expanded into operations on the set of nonempty subsets of {0,1,...,r-t}. These operations will be called regular since this method is identical with the way that Kleene expanded operations of binary logic into his ternary logic. Finally, explicit expressions of set-valued functions monotonic in ⊂ will be presented.
- 社団法人電子情報通信学会の論文
- 1999-10-25
著者
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Takagi Noboru
Department Of Electronics And Informatics Faculty Of Engineering Toyama Prefectural University
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Nakashima Kyoichi
Department Of Electronics And Informatics Faculty Of Engineering Toyama Prefectural University
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Nakashima Kyoichi
Department Of Electronics And Informatics Toyama Prefectural University
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Takagi Noboru
Department Of Electronics And Informatics Toyama Prefectural University
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- A Fail-Safe Condition for Multiple-Valued Logic Circuits Consisting of AND, OR and NOT Gates
- A Necessary and Sufficient Condition for Kleenean Functions
- Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits(Special Section on Papers Selected from ITC-CSCC 2002)
- A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations
- A Logical Model for Representing Ambiguous States in Multiple-Valued Logic Systems