A Design Hierarchy of IC Interconnects and Gate Patterns (Special Issue on TCAD for Semiconductor Industries)

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概要

• 論文の詳細を見る

• A new design hierarchy in TCAD is discussed with emphasis on a design of IC interconnects and gate patterns.Two design methodologies for gate patterns at a CMOS cell level and multilevel interconnect scheme at a chip level are proposed.This approach generates the layout design rules of gate patterns, considering the fabrication process and pattern layout dependency, and allows a design of multilevel interconnect scheme at the initial phase of technology development.

• 社団法人電子情報通信学会の論文
• 1999-06-25

著者

• YAMASHITA Kyoji

  ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electric Ind. Co., Ltd

• Odanaka Shinji

  Ulsi Process Technology Development Center Matsushita Electronics Corporation

• Misaka Akio

  Ulsi Process Technology Development Center Matsushita Electronics Corporation

• Yamashita Kyoji

  Ulsi Process Technology Development Center Matsushita Electronics Corporation

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• A Design Hierarchy of IC Interconnects and Gate Patterns (Special Issue on TCAD for Semiconductor Industries)
• Pocket Profiling of 0.1μm n-MOSFETs Using High Dose Indium Implantation
• Fundamental Study of the Mask Topography Effect on the Advanced Phase-Shifting Masks for Next-Generation Lithography

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