Pocket Profiling of 0.1μm n-MOSFETs Using High Dose Indium Implantation
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概要
- 論文の詳細を見る
- 1999-09-20
著者
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YAMASHITA Kyoji
ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electric Ind. Co., Ltd
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Odanaka Shinji
Ulsi Process Technology Development Center Matsushita Electronics Corporation
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Odanaka Shinji
Ulsi Process Technology Development Center Semiconductor Company Matsushita Electronics Corp.
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Hiroki Akira
Ulsi Process Technology Development Center Semiconductor Company Matsushita Electronics Corp.
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Yamashita Kyoji
Ulsi Process Technology Development Center Matsushita Electronics Corporation
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Yamashita Kyoji
Ulsi Process Technology Development Center Semiconductor Company Matsushita Electronics Corp.
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NAKANISHI Kentaro
ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electronics Corp.
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Nakanishi Kentaro
Ulsi Process Technology Development Center Semiconductor Company Matsushita Electronics Corp.
関連論文
- A Test Structure for Two-Dimensional Analysis of MOSFETs by Hot-Carrier-Induced Photoemission(Microelectronic Test Structures)
- A New Test Structure for Precise Location Measurement of Hot-Carrier-Induced Photoemission Peak in Subquarter-Micron MOSFETs(Special Issue on Microelectronic Test Structures)
- A Design Hierarchy of IC Interconnects and Gate Patterns (Special Issue on TCAD for Semiconductor Industries)
- Pocket Profiling of 0.1μm n-MOSFETs Using High Dose Indium Implantation