A Microprocessor Architecture Utilizing Histories of Dynamic Sequences Saved in Distributed Memories(Special Issue on Novel VLSI Processor Architectures)
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概要
- 論文の詳細を見る
In order to improve microprocessor performance, we propose to utilize histories of dynamic instruction sequences.A lot of special purpose memories integrated in a processor chip hold the histories.In this paper, we describe the usefulness of using two special purpopse memories:Non-Consecutive basic block Buffer(NCB)and Reference Prediction Table(RPT).The NCB improves instruction fetching efficiency in order to relive control dependences.The RPT predicts data addresses in order to speculate data dependences.From the simulation study, it has been found that the proposed mechanisms improve processor performance by up to 49.2%.
- 社団法人電子情報通信学会の論文
- 1998-09-25
著者
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Sato Toshinori
Kyushu Univ. Fukuoka‐shi Jpn
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Sato Toshinori
Department Of Artificial Intelligence Kyushu Institute Of Technology
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SATO Toshinori
The author is with Microelectronics Engineering Laborarory, Toshiba Corporation
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