An Energy-Efficient Clustered Superscalar Processor(Digital, <Special Section>Low-Power LSI and Low-Power IP)
スポンサーリンク
概要
- 論文の詳細を見る
Power consumption is a major concern in embedded microprocessors design. Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power. We evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is substantially energy-efficient while it suffers performance degradation.
- 社団法人電子情報通信学会の論文
- 2005-04-01
著者
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Sato Toshinori
Department Of Biosciences And Informatics Faculty Of Science And Technology Keio University
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Sato Toshinori
Kyushu Univ. Fukuoka‐shi Jpn
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Sato Toshinori
Department Of Artificial Intelligence Kyushu Institute Of Technology
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CHIYONOBU Akihiro
Department of Artificial Intelligence, Kyushu Institute of Technology
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Chiyonobu Akihiro
Fujitsu Ltd.. Kawasaki‐shi Jpn
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Sato Toshinori
Department of Applied Chemistry, Keio University
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