A Low-Power Instruction Issue Queue for Microprocessors

スポンサーリンク

概要

• 論文の詳細を見る

• Instruction issue queue is a key component which extracts instruction level parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction queue size should be increased. However, it is difficult to increase the size, since instruction queue is implemented by a content addressable memory (CAM) whose power and delay are much large. This paper introduces a low power and scalable instruction queue that replaces the CAM with a RAM. In this queue, instructions are explicitly woken up. Evaluation results show that the proposed instruction queue decreases processor performance by only 1.9% on average. Furthermore, the total energy consumption is reduced by 54% on average.

• （社）電子情報通信学会の論文
• 2008-04-01

著者

• SATO Toshinori

  Kyushu University

• WATANABE Shingo

  Kyushu Institute of Technology

• CHIYONOBU Akihiro

  Fujitsu Limited

• Sato Toshinori

  Kyushu Univ. Fukuoka‐shi Jpn

関連論文

• Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment
• Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment
• A Low-Power Instruction Issue Queue for Microprocessors
• An Energy-Efficient Clustered Superscalar Processor(Digital, Low-Power LSI and Low-Power IP)
• A Transparent Transient Faults Tolerance Mechanism for Superscalar Processors(Dependable Systems)(Dependable Computing)
• A Microprocessor Architecture Utilizing Histories of Dynamic Sequences Saved in Distributed Memories(Special Issue on Novel VLSI Processor Architectures)
• Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI

スポンサーリンク