A New FPGA Architecture for High Performance Bit-Serial Pipeline Datapath

概要

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In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel systems require large amount of routing resource which is especially critical in using FPGAs. Their device utilization and operation frequency become low because of large routing penalty. Whereas bit-serial circuits are very efficient in routing, therefore are able to achieve a very high logic utilization. Our proposed FPGA architecture is designed taking into account the structure of bit-serial circuits to optimize the logic and routing architecture. Our FPGA guarantees near 100% logic utilization with a straightformard place and route tool due to high routability of bit-serial circuits and simple routing interconnect architecture. The FPGA chip core which we designed consists of around 200k transistors on 3.5mm square substrate using 0.5μm 2-metal CMOS process technology.
社団法人電子情報通信学会の論文
2000-08-25