Electrical Overstress Failure Mechanism Investigation about High-power Scan Driver IC for Plasma Display Panel(Session A7 High Power Devices)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))

概要

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This paper will analyze mechanism for Y-scan buffer IC failure of Plasma Display Panel (PDF) using the Real-time Electrical Stress Analysis (RTESA) method. The Real-time Electrical Stress Analysis (RTESA) method is to show the phenomenon, in which electrical stress comes into an Integrated circuit (IC) in Device operating condition, as photoemission profile, connecting Photoemission Spectrum Analyzer (PSA) with External Electrical Stress source and Bias network. ln other words, this method is to find soft damage level, damage injection path, and damage mechanism easily by showing electrical stress effect procedure as photoemission profile. Failed high-power scan buffer IC is commercial IC of vender A, and scan buffer o f vender B which has the same function is analyzed for comparative verification. The equipment applied for analysis is the HP4155C semiconductor parameter, the Photoemission Spectrum Analyzer, an Optical Microscope, and an Electron Scanning Microscope. In this investigation, we could have verified phenomenon that EOS came into OUT influences on VDDH through experiment in demonstration using the Real-time Electrical Stress Analysis (RTESA) method.
社団法人電子情報通信学会の論文
2004-06-24