Reconsideration of Off-Leakage Current Estimation of Sub -100-nm SOI MOSFETs and Device Selection for Applications

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概要

• 論文の詳細を見る
• 関西大学の論文

著者

• Omura Yasuhisa

  Faculty Engineering

• Yanagi Shin-ichiro

  High-technology Research Center

関連論文

• A Partial-Ground-Plane (PGP) Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) for Deep Sub-0.1μm Channel Regime
• Proposal of a Partial-Ground-Plane(PGP) Silicon-on-Insulator(SOI) MOSFET for Deep Sub-100-nm Channel Regime
• Impact of transport noise enhancement in scaled-down MOSFET
• Noise characteristics and modeling of silicon-on-insulator insulated-gate pn-junction devices
• Consideration of Performance Limitation of Sub-100-nm Double-Gate Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) : Electnical Properties of Condensed Malter
• Reconsideration of Off-Leakage Current Estimation of Sub -100-nm SOI MOSFETs and Device Selection for Applications

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