A Fast Pull-In and Wide Locking Range All Digital FLL Using Pulse Counter
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概要
- 論文の詳細を見る
The frequency locked loop (FLL) can realize fast pull-in time and a wide lock range compared to a phase locked loop (PLL). However, since FLL has more problems than a PLL, it is not frequently used. In this paper, a simple all digital FLL (ADFLL) is proposed, which has a fast pull-in time and wide rock range. This circuit can detect frequency error within two cycle of output signal and one cycle of input signal later; therefore it can be realize a fast pull-in time. Since lock range is controlled by the division ratio of the programmable divider, this circuit has a wide lock range. This circuit will be integrated into silicon and operate at high-speed.
- 東海大学の論文
著者
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Fujimoto Kuniaki
School Of Engineering Kyushu Tokai University
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TAKAHASHI Nobuaki
Department of Applied Physics, National Defense Academy
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YAHARA Mitsutoshi
Tokai University Fukuoka Junior College
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YAHARA Mitsutoshi
Department of Information and Management Science, Tokai University Fukuoka Junior College
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SASAKI Hirofumi
Department of Electronics and Information Technology, School of Engineering, Kyushu Tokai University
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FUJIMOTO Kuniaki
Department of Electronics and Information Technology, School of Engineering, Kyushu Tokai University
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SASAKI Hirofumi
Tokai University
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Takahashi Nobuaki
Department Of Applied Physics National Defense Academy
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Takahashi Nobuaki
Department Of Electronics
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SASAKI Hirofumi
School of Engineering, Kyushu Tokai University
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