Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches
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概要
- 論文の詳細を見る
- 2011-12-07
著者
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ITOH Kouichi
FUJITSU LABORATORIES Ltd.
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YAMAMOTO Dai
FUJITSU LABORATORIES Ltd.
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TAKENAKA MASAHIKO
FUJITSU LABORATORIES LTD
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Sakiyama Kazuo
The University Of Electro-communications
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Ochiai Takao
Fujitsu Laboratories Ltd.
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Iwamoto Mitsugu
The University of Electro-Communications
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Ota Kazuo
The University of Electro-Communications
関連論文
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- Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher
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- Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm(Digital, Low-Power LSI and Low-Power IP)
- Theoretical Analysis of x^2 Attack on RC6 (Symmetric Cipher) (Cryptography and Information Security)
- Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches
- Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher
- Detailed Cost Estimation of CNTW Forgery Attack against EMV Signature Scheme
- Experimental Analysis of Cheon's Algorithm against Pairing-friendly Curves
- Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches
- Extending Bleichenbacher's Forgery Attack
- A New Type of Fault-Based Attack : Fault Behavior Analysis
- Correlation Power Analysis and Countermeasure on the Stream Cipher Enocoro-128v2