Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
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概要
- 論文の詳細を見る
- 2012-02-01
著者
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Hsu Wan-ling
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University
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Huang Juinn-dar
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University
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Lin Yen-ting
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University
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Chen Chia-i
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University
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Jou Jing-yang
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University
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- Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
- Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay