Internet-Based Hierarchical Floorplan Design (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• With the proliferation of the transistor count in VLSI design, more and more design groups try to figure out an efficient way to combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical design can adequately be solved in the Internet environment. In this paper, we demonstrate the facilitation of the Internet environment by solving the area minimization floorplan problem. We propose the RMG algorithm taking advantage of the Internet. Based on the model of transfer latencies, the RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. Our experimental results show that the Internet is suitable for Electronic Design Automation (EDA).

• 社団法人電子情報通信学会の論文
• 1999-11-25

著者

• Jiang Iris

  Department Of Electronics Engineering National Chiao Tung University

• Jou J‐y

  National Chiao‐tung Univ. Hsinchu Twn

• Jou Jing-yang

  Department Of Electronics Engineering National Chiao Tung University

• Lin Jiann-horng

  Department Of Electronics Engineering National Chiao Tung University

• Jou Jing-yang

  Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University

関連論文

• An Efficient Power Model for IP-Level Complex Designs (VLSI Design Technology and CAD)
• Internet-Based Hierarchical Floorplan Design (Special Section on VLSI Design and CAD Algorithms)
• Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay

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