Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture

スポンサーリンク

概要

• 論文の詳細を見る

• In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative algorithm with regard of both spatial and temporal perspectives. It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.

• （社）電子情報通信学会の論文
• 2009-12-01

著者

• Hong Yu-ju

  Department Of Electrical And Computer Engineering Purdue University

• Huang Ya-shih

  Department Of Electronics Engineering National Chiao Tung University

• HUANG Juinn-Dar

  Department of Electronics Engineering, National Chiao Tung University

• Huang Juinn-dar

  Department Of Electronics Engineering National Chiao Tung University

• Huang Juinn-dar

  Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University

関連論文

• Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
• A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication
• Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
• Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay

スポンサーリンク