Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture

スポンサーリンク

概要

• 論文の詳細を見る

• In deep-submicron era, wire delay is becoming a bottleneck while pursuing even higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most wires local. In this article, we propose a new resource-constrained communication synthesis algorithm for optimizing both inter-island connections (IICs) and latency targeting on distributed register-file microarchitecture (DRFM). The experimental results show that up to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work.

• 2011-04-01

著者

• Chen Chia-i

  Department Of Electronics Engineering And The Institute Of Electronics National Chiao Tung Universit

• Hsu Wan-ling

  Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University

• Huang Juinn-dar

  Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University

• Lin Yen-ting

  Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University

• Chen Chia-i

  Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University

関連論文

• Longitudinal Trends of Total White Blood Cell and Differential White Blood Cell Counts of Atomic Bomb Survivors
• White Blood Cell Count, Especially Neutrophil Count, as a Predictor of Hypertension in a Japanese Population
• Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
• A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication
• Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
• Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay

スポンサーリンク