High-Performance Architecture for Concurrent Error Detection for AES Processors
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概要
- 論文の詳細を見る
This paper proposes an efficient scheme for concurrent error detection for hardware implementations of the block cipher AES. In the proposed scheme, the circuit component for the round function is divided into two stages, which are used alternately for encryption (or decryption) and error checking in a pipeline. The proposed scheme has a limited overhead with respect to size and speed for the following reasons. Firstly, the need for a double number of clock cycles is eliminated by virtue of the reduced critical path. Secondly, the scheme only requires minimal additional circuitry for error detection since the detection is performed by the remaining encryption (or decryption) components within the pipeline. AES hardware with the proposed scheme was designed and synthesized by using 90-nm CMOS standard cell library with various constraints. As a result, the proposed circuit achieved 1.66Gbps @ 12.9 Kgates for the compact version and 4.22Gbps @ 30.7 Kgates for the high-speed version. These performance characteristics are comparable to those of a basic AES circuit without error detection, where the overhead of the proposed scheme is estimated to be 14.5% at maximum. The proposed circuit was fabricated in the form of a chip, and its error detection performance was evaluated through experiments. The chip was tested with respect to fault injection by using clock glitch, and the proposed scheme successfully detected and reacted to all introduced errors.
- 2011-10-01
著者
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AOKI Takafumi
Graduate School of Information Sciences, Tohoku University
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Aoki Takafumi
Tohoku Univ. Sendai‐shi Jpn
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Sugawara Takeshi
Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku Univ
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Aoki Takafumi
Department Of Computer And Mathematical Sciences Graduate School Of Information Science Tohoku Unive
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Satoh Akashi
Advanced Industrial Sci. And Technol. (aist) Tokyo Jpn
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Homma Naofumi
Tohoku Univ. Sendai‐shi Jpn
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Satoh Akashi
National Institute Of Advance Industrial Science And Technology
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SUGAWARA Takeshi
Tohoku University
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