Homma Naofumi | Tohoku Univ. Sendai‐shi Jpn

スポンサーリンク

概要

関連著者

もっと見る

著作論文

Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic(Novel Device Architectures and System Integration Technologies)
A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks
Arithmetic Circuit Verification Based on Symbolic Computer Algebra
Formal Design of Arithmetic Circuits Based on Arithmetic Description Language(Circuit Synthesis,VLSI Design and CAD Algorithms)
Counter Tree Diagrams : A Unified Framework for Analyzing Fast Addition Algorithms(IP Design)(VLSI Design and CAD Algorithms)
Parallel Evolutionary Design of Constant-Coefficient Multipliers
Evolutionary Synthesis of Fast Constant-Coefficient Multipliers
Evolutionary Design of Arithmetic Circuits (Special Section on Discrete Mathematics and Its Applications)
High-Performance Architecture for Concurrent Error Detection for AES Processors
A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments
Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current

もっと見る

スポンサーリンク