A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture

スポンサーリンク

概要

• 論文の詳細を見る

• This paper proposes a low-voltage high-speed sample-and-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-μm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of -67.3dB up to 250MSample/s and a 0.8VPP input range at 0.8V supply. The power consumption is 3.5mW and the figure-of-merit is only 7.4fJ/step.

• （社）電子情報通信学会の論文
• 2008-09-01

著者

• CHANG Soon-Jyh

  Department of Electrical Engineering, National Cheng Kung University

• Chang Soon-jyh

  Department Of Electrical Engineering National Cheng Kung University

• Chang Soon‐jyh

  Department Of Electrical Engineering National Cheng Kung University

• LIU Bin-Da

  Department of Electrical Engineering, National Cheng Kung University

• OU Hsin-Hung

  Department of Electrical Engineering, National Cheng Kung University

• Ou Hsin-hung

  Department Of Electrical Engineering National Cheng Kung University

• Liu Bin-da

  Department Of Electrical Engineering National Cheng Kung University

関連論文

• A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages
• A 5-bit 4.2-GS/s Flash ADC in 0.13-μm CMOS Process
• A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter
• A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture
• Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture
• Coefficients Generation for the 4th-Order Leapfrog Sigma-Delta A/D Converters (Analog Signal Processing)
• A 1.2V Rail-to-Rail Analog CMOS Rank Filter
• A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing
• An Analog CMOS Rank-Order Extractor with O(N) Complexity Using Maximum/Winner-Take-All Circuit(Integrated Electronics)
• A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding

スポンサーリンク