An Analog CMOS Rank-Order Extractor with O(N) Complexity Using Maximum/Winner-Take-All Circuit(Integrated Electronics)

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概要

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• In this paper, design of a new analog CMOS rank-order extractor with input expandable capability is described. An rth rank-order extraction is defined that identifies the rth largest magnitude of input variables, which is useful for fuzzy controller and artificial neural networks. The architecture is realized by using maximum circuit, winner-take-all circuit, and some auxiliary circuits. The limitations and design considerations of these circuits are analyzed in this paper. An experimental chip with seven inputs is fabricated using a 0.5 μm CMOS doublepoly double-metal technology. The results of measurement show the extractor with 2 μA precision, and each rank-order extraction has about 2 μs response time. The power dissipation of the experiment chip under test includes input/output pads that has 7.2mW for 3.3V supply voltage. The chip area of the extractor is 600 μm × 700 μm.

• 一般社団法人電子情報通信学会の論文
• 2003-08-01

著者

• Liu Bin-da

  Department Of Electrical Engineering National Cheng Kung University

• Hung Yu-cherng

  Department Of Electrical Engineering National Cheng Kung University

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• An Analog CMOS Rank-Order Extractor with O(N) Complexity Using Maximum/Winner-Take-All Circuit(Integrated Electronics)

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