HEMT Yield Improvement with Ultrasonic-assisted recess for High speed Integrated Circuit
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概要
- 論文の詳細を見る
- 2005-09-13
著者
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Yeon Seong-jin
Seoul National Univ. School Of Electrical Engineering And Computer Science
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Lee Jongwon
Seoul National Univ. School Of Electrical Engineering And Computer Science
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SEO Kwangseok
Seoul National Univ., School of Electrical Eng.
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Seo Kwangseok
Seoul National Univ. School Of Electrical Eng.
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KIM Hyungtae
Seoul National Univ., School Of Electrical Engineering and Computer Science
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Kim Hyungtae
Seoul National Univ. School Of Electrical Engineering And Computer Science
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YEON Seong-Jin
Seoul National Univ., School Of Electrical Engineering and Computer Science
関連論文
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- Compact RF Switches Using Dielectric Overhang Gate Process & Stacked Inductor
- In_GaP/Al_GaAs E-pHEMT with High Gate Forward Turn-on Voltage & High Transconductance Linearity
- Transconductance Linearity Improvement of Enhancement-Mode Pseudomorphic HEMT with High Gate Forward Turn-On Voltage
- Transconductance Linearity Improvement of E-pHEMT with High Vg.on
- High performance 0.1μm GaAs PHEMT with Si pulse doped cap layer for 77GHz car radar applications
- High performance 50nm In_Al_As/In_Ga_As Metamorphic HEMTs with Si_3N_4 passivation on thin InGaAs/InP layer
- High-Speed Digital Circuits Using RTD as Load-Element
- Novel MOBILE Circuits Using 3 RTDs Operating up to 12.5Gb/s
- High performance 70nm In_GaP/In_AlAs/In_GaAs Metamorphic HEMT With Pd Schottky Contacts
- The Gate Length Reducing Process for Pseudomorphic In_Al_As/In_Ga_As HEMTs
- HEMT Yield Improvement with Ultrasonic-assisted recess for High speed Integrated Circuit
- High-speed and Low-Power SCFL-Type NRZ Delayed Flip-Flop Circuit Using RTD/HEMT Integration Technology
- High-speed and Low-Power NRZ Delayed Flip-Flop Circuit Using RTD/HEMT Integration Technology
- Transconductance Linearity Improvement of Enhancement-Mode Pseudomorphic HEMT with High Gate Forward Turn-On Voltage