A Novel Cell Structure with Bit Line Cap Spacer (BCS) and Top Enlarged Storage Node Contact (TESC) for 90nm DRAM Technology and Beyond
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概要
- 論文の詳細を見る
- 2004-09-15
著者
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LEE S.
DRAM PM Center, Samsung Electronics Co.
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Kim S.
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Park Y.
Dram Process Architecture Team Samsung Electronics Co. Ltd.
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Lee S.
Dram Pm Center Samsung Electronics Co.
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Lee J.
Dram Process Architecture Team Samsung Electronics Co. Ltd.
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YUN C.
DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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BAE D.
DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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SHIN S.
DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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LEE D.
DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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LEE E.
DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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ROH B.
DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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NAM I.
DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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CHUNG T.
DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
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Kim S.
Dram Process Architecture Team Samsung Electronics Co. Ltd.
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Lee S.
Dram Process Architecture Team Samsung Electronics Co. Ltd.
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Shin S.
Dram Process Architecture Team Samsung Electronics Co. Ltd.
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Roh B.
Dram Process Architecture Team Samsung Electronics Co. Ltd.
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LEE J.
DRAM Process Architecture Team, Samsung Electronics Co., Ltd.
関連論文
- URCAT (U-shaped-Recess-Channel-Array Transistor) Technology for 60nm DRAM and beyond
- Cost-Effective and Highly Reliable 6F2 Multi-Gigabit DRAM in 60nm Technology Node for Low Power and High Performance Applications
- A Novel Cell Structure with Bit Line Cap Spacer (BCS) and Top Enlarged Storage Node Contact (TESC) for 90nm DRAM Technology and Beyond
- Robust TiN/AHO/HSG-Cylinder Capacitor for High Density DRAMs