位相状態記憶制御とダブルクロックエッジ検出に基づく分周比可変型ディジタルPLL

概要

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In this paper, we propose the dividing ratio changeable digital phase locked loop (PLL) based on phase state memory and double clock-edge detection in which satisfies three characteristics of a low jitter, wide lock-in range, and fast pull-in at the same time. The counter for the double edge detection of the base clock reduces the circuit scale by using the selector. In a steady state, the output jitter of the proposed digital PLL becomes always half pulse width of the base clock regardless of the frequency fluctuation of the base clock. Also, the upper bound frequency of the lock-in range becomes 6 times that of the conventional dividing ratio changeable digital PLL, when the permissible output jitter is identical. Furthermore, the fast pull-in is finishes in one period of the input signal and the pulse width of the multiplication output signal becomes almost constant.
社団法人電気学会の論文
2008-07-01