The Possibility of Quantized Conductance at Temperatures above 4.2K in Bulk Si MOSFETs

スポンサーリンク

概要

• 論文の詳細を見る
• 1995-08-21

著者

• Aoki Masaaki

  Central Research Laboratory Hitachi Ltd.

• Takeuchi Kan

  Central Research Laboratory Hitachi Ltd.

• HISAMOTO Dai

  Central Research Laboratory, Hitachi Ltd.

• YAMASHITA Hisaomi

  Hitachi VLSI Engineering Corp

• Hisamoto Dai

  Central Research Laboratory Hitachi Ltd.

関連論文

• Large 1/f Noise in Polysilicon TFT Loads and its Effects on the Stability of SRAM Cells
• Large 1/f Noise in Polysilicon TFT Loads and Its Effects on the Stability of SRAM Cells
• Fabrication of 0.1μm Complementary Metal-Oxide-Semiconductor Devices : Micro/nanofabrication and Devices
• Fabrication of 0.1μm Complementary Metal-Oxide-Semiconductor Devices
• Sub 1V Swing Internal Bus Architecture for Future Low-Power ULSI's (Special Section on the 1992 VLSI Circuits Symposium)
• Conductance Anomalies and Electronic States in Silicon Inversion Layers near Threshold at Low Temperatures
• The Possibility of Quantized Conductance at Temperatures above 4.2K in Bulk Si MOSFETs
• Large 1/f Noise in Polysilicon TFT Loads and its Effects on the Stability of SRAM Cells

スポンサーリンク