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ST Microelectronics | 論文
- A Breakthrough Electronic Lithography Process Through Si Layer for Self Aligning Gates in Planar Double-Gate Transistors for 32nm Node And Below
- CMP-less Co-Integration of Tunable Ni-TOSI CMOS for Low Power Digital and Analog Applications
- Si_Ge_x/Si Selective Etch with HCl for Thin Si-Channel Transistors Integration
- Highly scalable and WF-tunable Ni(Pt)Si / SiON TOSI-gate CMOS devices obtained in a CMP-less integration scheme
- Effect of Process Induced Strain in 35nm FDSOI Devices with Ultra-Thin Silicon Channels
- Strained-Si for CMOS 65nm node : Si_Ge_ SRB or "Low Cost" approach?
- A Novel Self Aligned Design Adapted Gate All Around (SADAGAA) MOSFET including two stacked Channels : A High Co-Integration Potential
- Analytical model for subband engineering in undoped double gate MOSFETs
- Using MASTAR as a Pre-SPICE Model Generator for Early Technology Assessment and Circuit Simulation
- 45nm Conventional Bulk and "Bulk+" Architectures for Low-Cost GP/LP Applications
- A Comprehensive Modeling Study of Two-Dimensional Silicon Subbands Using a Full-Zone k.p Method
- A Full Analytical Model to evaluate Strain Induced by CESL on MOSFET Performances
- In-situ comparison of Si/High-K and Si/SiO_2 interface properties in FD SOI MOSFETs operated at low temperature
- Control of Selectivity between SiGe and Si in Isotropic Etching Processes
- A Neural Network Based Behavioral Model of a Monolithic Cascode Power Switch
- A New Characterization Method for Accurate Capacitor Matching Measurements Using Pseudo-Floating Gate Test Structures in Submicron CMOS and BICMOS Technologies (Special Issue on Microelectronic Test Structures)