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Process Technology Development Division Renesas Technology Corp. | 論文
- Local Bonding Structure of High-Stress Silicon Nitride Film modified by UV Curing for Strained-Silicon Technology beyond 45nm Node SoC Devices
- Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-$k$/Metal Gate Transistor
- Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond
- Highly Reliable Cu Interconnect Using Low-Hydrogen Silicon Nitride Film Deposited at Low Temperature as Cu-Diffusion Barrier
- Effect of NH3-Free Silicon Nitride for Protection Layer of Magnetic Tunnel Junction on Magnetic Properties of Magnetoresistive Random Access Memory
- Effect of N2 Gas Flow Ratio in Plasma-Enhanced Chemical Vapor Deposition with SiH4–NH3–N2–He Gas Mixture on Stress Relaxation of Silicon Nitride
- Local Bonding Structure of High-Stress Silicon Nitride Film Modified by UV Curing for Strained Silicon Technology beyond 45 nm Node SoC Devices
- Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45 nm Node Devices and Beyond