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Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea | 論文
- 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
- Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
- Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
- 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
- Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
- An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
- Low Hysteresis Organic Thin-Film Transistors and Inverters with Hybrid Gate Dielectric
- Pentacene TFTs Fabricated by High-aspect Ratio Metal Shadow Mask
- Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
- Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
- Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
- Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
- Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
- Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
- Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
- Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
- Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
- Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)