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Department Of Electronic Engineering School Of Engineering The University Of Tokyo:vlsi Design And E | 論文
- A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells(Computer Components)
- A Logic-Cell-Embedded PLA (LCPLA) : An Area-Efficient Dual-Rail Array Logic Architecture(Integrated Electronics)
- Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
- Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
- A-3-7 A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells
- Wide Dynamic Range Photo Detector for Smart Position Sensor Using Log-Response and Correlation Circuit
- A Synchronous Completion Prediction Adder (SCPA)
- Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells(Circuit Synthesis, VLSI Design and CAD Algorithms)
- Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD)
- High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability(Physical Design)(VLSI Design and CAD Algorithms)
- Non-Approximate Evaluation of Macroscopic Quantum Tunneling of Charge for the Two-Junction Case at Arbitrary Temperatures and Bias Voltages
- Power Optimization for Data Compressors Based on a Window Detector in a 54 × 54 Bit Multiplier
- Fabrication of Step-Edge Junctions on the Concave or Convex Side of YBa_2Cu_3O_ Film
- A-3-12 A MONTE-CARLO ANALYSIS OF STATIC CMOS AND DUAL-RAIL PLA FOR SUB-100NM PARAMETER VARIATIONS