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Department Of Electrical And Computer Engineering University Of Utah | 論文
- Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation(Dependable Computing)
- Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model(Verification and Dependability Analysis)(Dependable Computing)
- Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
- Modular Synthesis of Timed Circuits Using Partial Order Reduction
- A Conservative Framework for Safety-Failure Checking
- Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times(System Level Design,VLSI Design and CAD Algorithms)
- Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits(Dependable Computing)
- Framework of Timed Trace Theoretic Verification Revisited(Special Issue on Test and Verification of VLSI)