Ikeda Makoto | Faculty of Engineering, and VLSI Design and Education Center (VDEC), the University of Tokyo
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- 同名の論文著者
- Faculty of Engineering, and VLSI Design and Education Center (VDEC), the University of Tokyoの論文著者
Faculty of Engineering, and VLSI Design and Education Center (VDEC), the University of Tokyo | 論文
- Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability
- Cascaded Time Difference Amplifier with Differential Logic Delay Cell
- 1.0ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells
- A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells(Computer Components)
- A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits(Integrated Electronics)