Sakamoto M | Mitsubishi Electric Corp. Itami‐shi Jpn
スポンサーリンク
概要
Mitsubishi Electric Corp. Itami‐shi Jpn | 論文
- Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application(Special Issue on Integrated Systems with New Concepts)
- A Sub 1-V L-Band Low Noise Amplifier SOI CMOS(Special Section on Analog Circuit Techniques and Related Topics)
- A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
- Analysis of the Delay Distributions of 0.5μm SOI LSIs (Special Issue on SOI Devices and Their Process Technologies)
- Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits (Special Issue on Low-power LSIs and Technologies)