SHISHIGUCHI Seiichi | Association of Super-advanced Electronics Technologies (ASET)

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概要

• 同名の論文著者
• Association of Super-advanced Electronics Technologies (ASET)の論文著者

関連著者

• SHISHIGUCHI Seiichi

  Association of Super-advanced Electronics Technologies (ASET)

• Yokoyama Shin

  Research Center For Integrated Systems Hiroshima University

• Matsuda T

  Diax Co. Ltd. Kasugai Jpn

• MINEJI Akira

  Advanced Technology Development Division, NEC Electronics Corporation

• MATSUDA Tomoko

  Advanced Technology Development Division, NEC Electronics Corporation

• Mineji Akira

  Advanced Technology Development Division Nec Electronics Corporation

• Matsuda Tomoko

  Advanced Technology Development Division Nec Electronics Corporation

• Imai Kiyotaka

  Ulsi Device Development Laboratories Nec Corporation

• Kuroki Shin-ichiro

  Research Center For Nanodevices And Systems Hiroshima University

• Shibahara Kentaro

  Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashihiroshima, Hiroshima 739-8527, Japan

• Shibahara Kentaro

  Reseach Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashihiroshima, Hiroshima 739-8527, Japan

• Kuroki Shin-Ichiro

  Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-Hiroshima 739-8527, Japan

• Kochiya Hiroyuki

  Association of Super-Advanced Electronics Technologies, Yokohama Research Center, 292 Yoshida-cho Totsuka-ku, Yokohama, Kanagawa 244-0817, Japan

• Kikkawa Takamaro

  Research Center for Nanodevice and Systems (RCNS), Hiroshima University, Higashihiroshima, Hiroshima 739-8527, Japan

• Imai Kiyotaka

  ULSI Device Development Division, NEC Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan

• IMAI Kiyotaka

  ULSI Device Development Division, NEC Corporation

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著作論文

• Optimized Source/Drain Ion Implantation Conditions for P-Channel Metal-Oxide-Semiconductor Field-Effect-Transistor Formation
• Phosphorus-Assisted Low-Energy Arsenic Implantation Technology for N-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Source/Drain Formation Process
• Low-$k$ Dielectric Film Patterning by X-Ray Lithography

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