OTSUGA Kazuo | Central Research Laboratory, Hitachi, Ltd.
スポンサーリンク
概要
関連著者
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Kurata Hideaki
Central Research Laboratory Hitachi Ltd.
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OTSUGA Kazuo
Central Research Laboratory, Hitachi, Ltd.
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Otsuga Kazuo
Central Research Laboratory Hitachi Ltd.
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KOBAYASHI Takashi
Central Research Laboratory, Hitachi Ltd.
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NODA Satoshi
Renesas Technology Corp.
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SASAGO Yoshitaka
Central Research Laboratory, Hitachi, Ltd.
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ARIGANE Tsuyoshi
Central Research Laboratory, Hitachi, Ltd.
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KAWAMURA Tetsufumi
Central Research Laboratory, Hitachi, Ltd.
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Kawamura Tetsufumi
Central Research Laboratory Hitachi Ltd.
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Kobayashi Takashi
Central Research Laboratory Hitachi Ltd.
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Otsuga Kazuo
Hitachi Ltd. Kokubunji‐shi Jpn
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Noda Satoshi
Renesas Technology Corporation
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Kurata Hideaki
Hitachi Ltd. Kokubunji‐shi Jpn
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Sasago Yoshitaka
Central Research Laboratory Hitachi Ltd.
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Arigane Tsuyoshi
Central Research Laboratory Hitachi Ltd.
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KAJIYAMA Shinya
Central Research Laboratory, Hitachi, Ltd.
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Sakamoto Yoshinori
Renesas Technology Corp.
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Ito Teruhiko
Renesas Technology Corp.
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KUME Hitoshi
Central Research Laboratory, Hitachi Ltd.
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ISHIKAWA Kiyoshi
Renesas Technology Corporation
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HOMMA Kazuki
Renesas Technology Corp.
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SHIMIZU Masahiro
Renesas Technology Corp.
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IKEDA Yoshinori
Renesas Technology Corp.
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TSUCHIYA Osamu
Renesas Technology Corp.
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FURUSAWA Kazunori
Hitachi ULSI Systems Co., Ltd.
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Kajiyama Shinya
Central Research Laboratory Hitachi Ltd.
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Kume Hitoshi
Central Research Laboratory Hitachi Ltd.
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Kume Hitoshi
Central Research Laboratory
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Kajiyama Shinya
Hitachi Ltd. Kokubunji‐shi Jpn
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Ishikawa Kiyoshi
Renesas Technol. Corp. Itami‐shi Jpn
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Furusawa Kazunori
Hitachi Ulsi Systems Co. Ltd.
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Sonoda Ken'ichiro
Central Research Laboratory Hitachi Ltd.
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KURATA Hideaki
Central Research Laboratory, Hitachi, Ltd.
著作論文
- A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model
- A 126mm^2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology(Integrated Electronics)
- Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories(Memory,Low-Power, High-Speed LSIs and Related Technologies)