Scaling Analysis of Nanoelectromechanical Memory Devices

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概要

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• Numerical simulation of electromechanical switching for bistable bridges in non-volatile nanoelectromechanical (NEM) memory devices suggests that performance of memory characteristics enhanced by decreasing suspended floating gate length. By conducting a two-dimensional finite element electromechanical simulation combined with a drift-diffusion analysis, we analyze the electromechanical switching operation of miniaturized structures. By shrinking the NEM floating gate length from 1000 to 100 nm, the switching (set/reset) voltage reduces from 7.2 to 2.8 V, switching time from 63 to 4.6 ns, power consumption from 16.9 to 0.13 fJ. This indicates the advantage of fast and low-power memory characteristics.

• 2010-04-25

著者

• Tsuchiya Yoshishige

  School Of Electronics And Computer Science University Of Southampton

• Uchida Ken

  Quantum Nanoelectronics Research Center and Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1 O-Okayama, Meguro, Tokyo 152-8552, Japan

• Shunri Oda

  Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro, Tokyo 152-8552, Japan

• Hiroshi Mizuta

  School of Electronics and Computer Science, University of Southampton, Highfield, Southampton, Hampshire SO17 1BJ, U.K.

• Nagami Tasuku

  Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan

• Tasuku Nagami

  Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan

• Yoshishige Tsuchiya

  School of Electronics and Computer Science, University of Southampton, SO17 1BJ Southampton, U.K.

• Shunri Oda

  Quantum Nanoelectronics Research Center, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan

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