Advanced Air Gap Process for Multi-Level-Cell Flash Memories Reducing Threshold Voltage Interference and Realizing High Reliability
スポンサーリンク
概要
- 論文の詳細を見る
As the cell size of flash memories is scaled down, the reading error due to threshold voltage ($V_{\text{th}}$) interference has become a more serious problem, particularly in the case of multi-level-cell (MLC) flash memories, it is necessary for the $V_{\text{th}}$ distribution to be narrower than that of the single-level-cell (SLC). In this work, we propose an advanced air gap structure and process to reduce the interference due to the capacitance between floating gate and floating gate. By applying an air gap between neighboring floating gates as a lowest-dielectric-constant material, we can suppress $V_{\text{th}}$ interference markedly. In addition, we clarified the correlation between the air gap forming process and the memory cell reliability. Hydrogen included in the SiO2 film, which is deposited by plasma-enhanced chemical vapor deposition (CVD) during air gap formation causes the degradation of memory cell endurance and the de-trapping characteristics. We were able to achieve a high-reliability memory cell by reducing the hydrogen concentration in the SiO2 by optimizing the deposition process for air gap formation.
- 2007-04-30
著者
-
SHIMIZU Masahiro
Renesas Technology Corp.
-
TSUCHIYA Osamu
Renesas Technology Corp.
-
YOSHITAKE Takayuki
Renesas Technology Corp.
-
Ikeda Yoshihiro
Renesas Technology Corporate, 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan
-
Tsukamoto Keisuke
Renesas Technology Corporate, 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan
-
Murata Tatsunori
Renesas Technology Corporate, 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan
-
Fukumura Tatsuya
Renesas Technology Corporate, 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan
-
Ohta Fumihito
Renesas Technology Corporate, 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan
-
Shimizu Satoshi
Renesas Technology Corporate, 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan
-
Asai Koyu
Renesas Technology Corporate, 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan
-
Asai Koyu
Renesas Electronics Corporation, 751 Horiguchi, Hitachinaka, Ibaraki 312-8504, Japan
関連論文
- A 126mm^2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology(Integrated Electronics)
- A 130-nm CMOS 95-mm^2 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput(Integrated Electronics)
- Advanced Air Gap Process for Multi-Level-Cell Flash Memories Reducing Threshold Voltage Interference and Realizing High Reliability
- Analytical Approach for Enhancement of n-Channel Metal--Oxide--Semiconductor Field-Effect Transistor Performance with Carbon-Doped Source/Drain Formed by Molecular Carbon Ion Implantation and Laser Annealing
- Characterizations of NiSi2-Whisker Defects in n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with $\langle 110\rangle$ Channel on Si(100)
- Analysis of sidewall damage layer in low-k film using the interline dielectric capacitance measurements (Special issue: Advanced metallization for ULSI applications)
- Narrow Line Effect of Nickel Silicide on p+ Active Lines and Its Suppression by Fluorine Ion Implantation
- Anomalous Nickel Silicide Encroachment in n-Channel Metal–Oxide–Semiconductor Field-Effect Transitors on Si(110) Substrates and Its Suppression by Si+ Ion-Implantation Technique